1. Field of the Invention
The present invention relates to a data processing unit having a data transfer function using a DMA (Direct Memory Access) controller.
2. Description of Related Art
FIG. 3 is a block diagram showing a conventional data processing unit shown on pp. 2-7 in "Mitsubishi 32-bit Single-Chip Microcomputer M16-Family/M10/10 Series User's Manual", published by Mitsubishi Denki Kabishiki Kaisha. In this figure, the reference numeral 1 designates a data processing unit, 3 designates a CPU connected to a bus 2, 4 designates an internal memory such as a ROM or RAM accessed by the CPU 3, 5 designates a DMA controller (referred to as DMAC from now on) having a data transfer function, 6 designates I/O equipment connected to the bus 2, 7 designates a storage accessed by the DMAC 5 and CPU 3, and 8 designates an external memory such as a RAM connected to the bus 2.
Next, the operation will be described.
When the CPU 3 reads a program stored in the internal memory 4 to execute it, the CPU 3 must acquire the right of using the bus 2 before accessing the internal memory 4.
Thus, the CPU 3 issues the access request to the bus 2 to acquire the right of using the bus 2.
If the DMAC 5 disables the access request as at points A, B and E in FIG. 4, and hence does not have the right of using the bus 2, the CPU 3 can acquire the right of using the bus 2 immediately. Thus, the CPU 3 places read addresses onto the bus 2 to carry out a read processing of the program from the internal memory 4.
However, if the DMAC 5 currently enables the access request and has the right of using the bus 2, the CPU 3 cannot acquire the right of using the bus 2, thereby entering a waiting state for the DMAC 5 to complete the data transfer and relinquish the right of using the bus 2.
The reason why the CPU 3 cannot acquire the right of using the bus 2 in spite of enabling the access request at the same time with the DMAC 5 is that the DMAC 5 has a higher priority to acquire the bus than the CPU 3.
Incidentally, the same reason applies to the fact that the DMAC 5 acquires the right of using the bus 2 three straight times by successively enabling the access requests (D2, D3 and D4) after having acquired the right of using the bus 2 at the point C.
After the DMAC 5 disables the access request to relinquish the right of using the bus 2 as at the point D in FIG. 4, the CPU 3 immediately acquires the right of using the bus 2.
Then, the CPU 3 places read addresses of the program onto the bus 2 to execute the read processing of the program from the internal memory 4.
With such an arrangement, the conventional data processing unit has a problem in that the CPU 3 cannot acquire the right of using the bus 2 as long as the DMAC 5 has it, thereby reducing the operating ratio of the CPU 3.